top of page
Create Your First Project
Start adding your projects to your portfolio. Click on "Manage Projects" to get started
CMOS 45nm D-FlipFlop
Subtitle: VSLI, Cadence
Description: Built and simulated a CMOS 45nm D-FlipFlop using Cadence's free 45nmPDK Library Suite, optimizing NMOS and PMOS sizing for cleaner signals and symmetrical fall-rise delays.
Report: https://docs.google.com/document/d/1k5kGwkX6swKN3ZNdSc8DymlLXmMLy7Qxu7OkwmZIjFc/edit?usp=share_link
bottom of page