Senior Design Project: RISCV-NPU-DualCore

This project involved the design and implementation of a custom pipelined RISC-V processor on an FPGA, with additional features and expansions that enhanced its functionality and performance. The processor was based on the RISC-V RV32IM instruction set architecture (ISA) and was custom-designed using references from the textbook Computer Organization and Design RISC-V Edition: The Hardware/Software Interface by David A. Patterson and John L. Hennessy (2nd Edition, 2020). The design featured a five-stage pipeline (Fetch, Decode, Execute, Memory Access, Writeback) tailored to maximize performance while adhering to the principles outlined in the textbook. The processor was implemented entirely in a hardware description language (VHDL), simulated using System Verilog, and tested extensively through simulation tools, testbenches, and bare metal runs.

To enhance usability, UART communication was integrated into the system to allow dynamic loading of the instruction buffer. This feature enabled programs to be loaded and executed without reprogramming the FPGA, greatly improving development efficiency and flexibility. For further expansion of the project’s feature set, MobileNet20—a convolutional neural network (CNN)—was implemented and executed on an upgraded Zybo Z7-7020 development board from Digilent. This marked a significant improvement over the previously used MiniZed board from AVNet, as the Zybo Z7-7020 provided increased computational power and I/O capabilities. The expanded system incorporated the PCAM5C camera module alongside Vivado’s video IP cores to process image data. This image data was fed into MobileNet20 for CNN-based recognition tasks, with classification results printed to a serial terminal for real-time observation.

The integration of the PCAM5C camera and Vivado’s video IP allowed for live image acquisition, which was processed by MobileNet20 running on the FPGA. The results demonstrated successful execution of CNN-based image recognition tasks directly on the hardware platform. This project not only showcased a robust implementation of a pipelined RISC-V processor but also highlighted its versatility in handling advanced applications such as real-time computer vision.

Github: https://github.com/CypherVault/RiscV-NPU-DualCore

See our poster for the project here: https://drive.google.com/file/d/1uXUdtd2Rv5fpQPT_xLQtQzXr7T_bFLpl/view?usp=share_link

See the report written here: https://docs.google.com/document/d/1UbhaGOq-ym8eUAlIEWyqDH5GJB_rbLEFv8ns1tZdF00/edit?usp=share_link