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SIMD Processor Design Project

Subtitle: VHDL, CAD
Description: Junior year VHDL hardware description language + modern CAD tool project of the structural and behavioral design of a four-stage pipelined multimedia unit with a reduced set of multimedia instructions similar to those in the Sony Cell SPU and Intel SSE architectures.

Github:https://github.com/CypherVault/ESE-345-PMU-PROJECT

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